Electrostatic discharge protection device and circuit thereof

ABSTRACT

An electrostatic discharge (ESD) protection circuit including a detection circuit for detecting the ESD current and a clamp circuit for bypassing an ESD current between a first pad and a second pad is provided. The detection circuit is connected between the first pad and the second pad, wherein the detection circuit comprises a diode and a variable resistor tuned by a diode, and an output terminal of the detection circuit is connected to the variable resistor. The clamp circuit is connected between the first pad and the second pad and connected to the output terminal of the detection circuit. When the ESD current from the first pad or the second pad is detected by the detection circuit, a trigger voltage is generated to trigger the clamp circuit to bypass the ESD current due to a resistance of the variable resistor is changed by the diode.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of a prior application Ser.No. 10/710,695, filed Jul. 29, 2004.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to an electrostatic discharge (ESD)protection device and circuit thereof. More particularly, the presentinvention relates to an ESD protection device and circuit thereof forbypassing an ESD current with higher shunting efficiency, faster turn-onefficiency and lower power consumption.

2. Description of Related Art

As the semiconductor technology advances, the integration of thesemiconductor devices are enhanced by, for example, reducing the linewidth and increasing the stacked layers of the semiconductor device. Forexample, as the scale of the metal on oxide semiconductor (MOS) deviceis reduced, the gate oxides has to be thinner, the channel length has tobe shorter, the source/drain junction has to be shallower, and thelightly doped drain (LDD) structure has to be adopted. However, as thearea and the tolerance of the integrated circuits (IC) reduce, thedamage caused by the electrostatic discharge (ESD) could become aserious problem.

Conventionally, the waveform of the electrostatic discharge (ESD) hasthe properties of short rise time (e.g., generally between 5 ns to 15ns) and high pulse power (e.g., generally between 1000V to 3000V).Therefore, when the integrated circuit (IC) is damaged by the ESD, theIC might get punched through or burned out suddenly.

In general, in order to resolve the problems described above, an ESDprotection circuit is generally disposed between the input and outputpads of the IC to protect the IC from the ESD damage by shunting theelectrostatic charges of the ESD source from the IC.

FIG. 1 is a circuit diagram schematically illustrating a conventionalESD protection circuit of an IC. Referring to FIG. 1, an ESD protectioncircuit 100 including a gate-ground NMOS (GGNMOS) 108 is connectedbetween two pads 104 and 106 of the IC 102. The pad 104 is connected toa voltage VDD and the pad 106 is connected to a voltage VSS. The drainof the GGNMOS 108 is connected to the pad 104 and the source, the gateand the substrate of the GGNMOS 108 are connected to the pad 106. Ingeneral, when a positive ESD voltage is suddenly applied across the pads104 and 106, a parasitic bipolar transistor 110 (illustrates as dottedlines 110 in FIG. 1) of the GGNMOS 108 is performed to bypass the ESDcurrent. Alternatively, when a negative ESD voltage is applied suddenlyacross the pads 104 and 106, a parasitic diode (illustrated as dottedlines 112 in FIG. 1, which exists everywhere in the drain/substratejunction of the integrated circuits (IC) 102 or in the ESD protectioncircuit 100) is forward biased and therefore is turned on to bypass theESD current. Generally, the performance of the ESD protection circuit100 including the GGNMOS 108 shown in FIG. 1 is not effective enough toprotect the IC 102. In addition, the turn-on efficiency of the GGNMOS108 is not fast enough.

FIG. 2A and FIG. 2B are circuit diagrams schematically illustratinganother conventional ESD protection circuit of an IC. Referring to FIG.2A and FIG. 2B, an ESD protection circuit 200 is connected between twopads 204 and 206 of the IC 202. The pad 204 is connected to a voltageVDD and the pad 206 is connected to a voltage VSS. The ESD protectioncircuit 200 includes a gate-ground NMOS (GGNMOS) 208, a resistor 210, acapacitor 212 and an inverter 214. The drain of the GGNMOS 208 isconnected to the pad 204, the source and the gate of the GGNMOS 208 areconnected to the pad 206, and the substrate of the GGNMOS 208 isconnected to the output terminal of the inverter 214. The resistor 210is connected between the pad 204 and the input of the inverter 214, andthe capacitor 212 is connected between the pad 206 and the inputterminal of the inverter 214. Referring to FIG. 2B, the inverter 214 maybe constructed by a PMOS 214 a and an NMOS 214 b. The gates of the PMOS214 a and the NMOS 214 b are connected to and used as the input terminalof the inverter 214, and the drains of the PMOS 214 a and the NMOS 214 bare connected to and used as the output terminal of the inverter 214.The sources of the PMOS 214 a and the NMOS 214 b are connected to thepads 204 and 206 respectively.

Referring to FIG. 2A or FIG. 2B, the resistance-capacitance (RC)constant (i.e., the resistance R of the resistor 210 and the capacitanceC of the capacitor 212, wherein the rise time of the RC constant isgenerally between 0.1 μs to 1 μs) is generally much larger than the risetime of the ESD voltage (generally between 5 ns to 15 ns). Therefore,when a positive ESD voltage is suddenly applied across the pads 204 and206, the input voltage V1 at the input terminal of the inverter 214 isat low level compared to the voltage VDD due to the larger RC constant.Thus, the output voltage V2 at the output terminal of the inverter 214is at high level since the voltage V1 is inverted by the inverter 214.Accordingly, the GGNMOS 208 will function as a bipolar transistor 110(as illustrated by the dotted lines 110 in FIG. 1) and is triggered bythe high level output voltage V2 to bypass the ESD current.

Alternatively, when a negative ESD voltage is suddenly applied acrossthe pads 104 and 106, a parasitic diode (as illustrated by the dottedlines 112 in FIG. 1, which exists everywhere in the drain/substratejunction of the integrated circuits (IC) 202 or in the ESD protectioncircuit 200) is forward biased and therefore is turned on to bypass theESD current. However, as the semiconductor technology advances, theintegration of the semiconductor device is enhanced and the tolerance ofthe semiconductor device to the ESD current is reduced, and theconventional ESD protection circuit design may not be effective inprotecting the advanced semiconductor device with low tolerance to ESDcurrent. Therefore, an ESD protection circuit with higher performance,higher shunting efficiency, faster turn-on efficiency and lower powerconsumption is highly desirable.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to electrostaticdischarge (ESD) protection device with higher performance, highershunting efficiency, faster turn-on efficiency and lower powerconsumption capable of bypassing an ESD current.

In addition, the present invention is also directed to electrostaticdischarge (ESD) protection circuit with higher performance, highershunting efficiency, faster turn-on efficiency and lower powerconsumption capable of bypassing an ESD current.

According to one embodiment of the present invention, an electrostaticdischarge (ESD) protection device comprising, for example but notlimited to, a detection device for detecting the ESD current and a clampdevice for bypassing the ESD current, is provided. The detection deviceis connected between the first pad and the second pad, wherein thedetection device comprises a diode and a variable resistor tuned by thediode, and an output terminal of the detection device is connected tothe variable resistor. The clamp device is connected between the firstpad and the second pad, and is connected to the output terminal of thedetection device. When the ESD current from the first pad or the secondpad is detected by the detection device, a trigger voltage is generatedto trigger the clamp device to bypass the ESD current due to aresistance of the variable resistor is changed by the diode.

In one embodiment of the present invention, the first pad and the secondpad are selected from a group consisting of a VDD pad and a VSS padalternatively.

In one embodiment of the present invention, the detection devicecomprises a first N-type metal oxide semiconductor (NMOS) transistorcomprising a drain connected to the first pad, a source connected to theoutput terminal of the detection device, a substrate connected to thesecond pad, and a gate connected to an output terminal of the diode,wherein an input terminal of the diode is connected to the second pad,and the variable resistor is connected between the output terminal ofthe detection device and the second pad.

In one embodiment of the present invention, the detection device furthercomprises a capacitor connected between the first pad and the gate ofthe first NMOS transistor, and a resistor connected between the secondpad and the gate of the first NMOS transistor. In still anotherembodiment of the present invention, the clamp device comprises a secondNMOS transistor comprising a drain connected to the first pad, a sourceconnected to the second pad, a substrate connected to the outputterminal of the detection device, and a gate connected to the substrateof the second NMOS transistor or the second pad.

In one embodiment of the present invention, the clamp device may furthercomprise a first P+ region in the substrate between the diode and thesource region of the second NMOS transistor.

In one embodiment of the present invention, the detection devicecomprises a bipolar PNP transistor comprising an emitter connected tosource of the first NMOS transistor, a base connected to the second pad,and a collector connected to the output terminal of the detectiondevice. In another embodiment of the present invention, the clamp devicecomprises a second NMOS transistor comprising a drain connected to thefirst pad, a source connected to the base of the bipolar PNP transistor,a substrate connected to the output terminal of the detection device,and a gate connected to the second pad. In still another embodiment ofthe present invention, the detection device comprises a capacitorconnected between the first pad and the gate of the first NMOStransistor, and a resistor connected between the second pad and the gateof the first NMOS transistor.

In one embodiment of the present invention, the clamp device comprises asecond NMOS transistor comprising a drain connected to the first pad, asource connected to the second pad, a substrate connected to the outputterminal of the detection device, and a gate connected to the substrateof the second NMOS transistor or the second pad.

According to one embodiment of the present invention, an electrostaticdischarge (ESD) protection circuit for bypassing an ESD current betweena first pad and a second pad is provided. The ESD protection circuitcomprises, for example but not limited to, a P-type substrate, a diode,a N-type metal oxide semiconductor (NMOS) transistor, a first P+ regionand a second P+ region. The diode comprises, for example but not limitedto, a first N-well region in the substrate and a N+ region in the firstN-well region. The NMOS transistor comprises, for example but notlimited to, a drain region in the substrate and connected to the firstpad, a source region in the substrate and connected to the second pad, agate formed over a portion of the drain region, a portion of the sourceregion and the substrate there-between. The first P+ region is formed inthe substrate between the first N-well region and the source region ofthe NMOS transistor, and the second P+ region is formed in the substrateat the other side of the first N-well region. The gate region of theNMOS transistor is connected to the first P+ region or the second P+region, and the second P+ region is connected to the second pad.

In one embodiment of the present invention, when the ESD current isdetected from the first pad or the second pad, a trigger voltage isgenerated to trigger the NMOS transistor to bypass the ESD current dueto a resistance of substrate around the first N-well is changed by thediode.

In one embodiment of the present invention, the first pad and the secondpad are selected from a group consisting of a VDD pad and a VSS padalternatively.

In one embodiment of the present invention, the ESD protection circuitfurther comprises another NMOS transistor comprising a drain regionconnected to the first pad, a source region connected to the first P+region, a substrate region connected to the second pad, and a gateregion connected to the N+ region of the first N-well.

In one embodiment of the present invention, the ESD protection circuitfurther comprises a capacitor connected between the first pad and thegate region of the another NMOS transistor, and a resistor connectedbetween the second pad and the gate region of the another NMOStransistor.

In one embodiment of the present invention, the ESD protection circuitfurther comprises a second N-well region formed in the substrate andincludes the first P+ region and a portion of the source region of theNMOS transistor. In addition, a bipolar PNP transistor comprising anemitter, a base and a collector is constructed by the first P+ region,the source region of the NMOS transistor, and a portion of the substrateunder the first P+ region respectively . In another embodiment of thepresent invention, the ESD protection circuit further comprises acapacitor connected between the first pad and the gate region of anotherNMOS transistor, and a resistor connected between the second pad and thegate region of the other NMOS transistor.

According to one embodiment of the present invention, an electrostaticdischarge (ESD) protection circuit comprising, for example, a P-typesubstrate, a NMOS transistor, a first P+ region and a second P+ region,and a second N-well region is provided. The NMOS transistor may comprisea drain region in the substrate and connected to the first pad, a sourceregion in the substrate and connected to the second pad, and a gateformed over a portion of the drain region, a portion of the sourceregion and the substrate there-between. The first P+ region may beformed in the substrate besides the source region and opposite to thedrain region of the NMOS transistor. The second P+ region may be besidesthe first P+ region. The gate region of the NMOS transistor is connectedto the first P+ region or the second P+ region and the second P+ regionis connected to the second pad. The second N-well region may beformed inthe substrate and includes the first P+ region and a portion of thesource region of the NMOS transistor. In addition, when the ESD currentfrom the first pad or the second pad is detected, a trigger voltage isgenerated to trigger the NMOS transistor to bypass the ESD current.

In one embodiment of the present invention, a bipolar PNP comprising anemitter, a base and a collector may be constructed by the first P+region, the source region of the NMOS transistor, and a portion of thesubstrate under the first P+ region respectively.

In one embodiment of the present invention, the first pad and the secondpad are selected from a group consisting of a VDD pad and a VSS padalternatively.

In one embodiment of the present invention, the ESD protection circuitmay further comprises another NMOS transistor comprising a drain regionconnected to the first pad, a source region connected to the first P+region, a substrate region connected to the second pad, and a gateregion connected to the second pad. In addition, the ESD protectioncircuit may further comprises a capacitor connected between the firstpad and the gate region of the another NMOS transistor, and a resistorconnected between the second pad and the gate region of the another NMOStransistor.

Accordingly, in the ESD protection circuit of the present invention,since a variable transistor tuned by a diode is provided for thedetection circuit to trigger the clamp circuit to bypass the ESDcurrent, the turn-on efficiency and the shunting efficiency of the clampcircuit is enhanced. Therefore, the performance of the ESD protectioncircuit is also enhanced and the power consumption of the ESD protectioncircuit is reduced.

One or part or all of these and other features and advantages of thepresent invention will become readily apparent to those skilled in thisart from the following description wherein there is shown and describeda preferred embodiment of this invention, simply by way of illustrationof one of the modes best suited to carry out the invention. As it willbe realized, the invention is capable of different embodiments, and itsseveral details are capable of modifications in various, obvious aspectsall without departing from the invention. Accordingly, the drawings anddescriptions will be regarded as illustrative in nature and not asrestrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a circuit diagram schematically illustrating a conventionalESD protection circuit of an IC.

FIG. 2A and FIG. 2B are circuit diagrams schematically illustratinganother conventional ESD protection circuit of an IC.

FIG. 3A is a circuit diagram of an ESD protection circuit according toone embodiment of the present invention.

FIG. 3B is a schematic cross-sectional view of an ESD protection circuitaccording to one embodiment of the present invention.

FIG. 4A is a circuit diagram of an ESD protection circuit according toone embodiment of the present invention.

FIG. 4B is a schematic cross-sectional view of an ESD protection circuitaccording to one embodiment of the present invention.

FIG. 5A is a circuit diagram of an ESD protection circuit according toone embodiment of the present invention.

FIG. 5B is a schematic cross-sectional view of an ESD protection circuitaccording to one embodiment of the present invention.

FIG. 5C is a circuit diagram of an ESD protection circuit according toanother embodiment of the present invention.

FIG. 5D is a schematic cross-sectional view of an ESD protection circuitaccording to another embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as limited to theembodiments set forth herein; rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. Likenumbers refer to like elements throughout.

FIG. 3A is a circuit diagram of an ESD protection circuit according toone embodiment of the present invention. FIG. 3B is a schematiccross-sectional view of an ESD protection circuit according to oneembodiment of the present invention. Referring to FIG. 3A, an ESDprotection circuit 300 is connected between two pads 304 and 306 of theIC 302. The pad 304 is connected to a voltage VDD and the pad 306 isconnected to a voltage VSS. The ESD protection circuit 300 comprises,for example but not limited to, a detection circuit 308 and a clampcircuit 310. Both of the detection circuit 308 and the clamp circuit 310are connected between the pads 304 and 306 respectively, and the clampcircuit 310 is connected to the detection circuit 308.

Referring to FIG. 3A, the detection circuit 308 comprises, for examplebut not limited to, a variable resistor Rv, a diode 312, a transistor314, a capacitor 316 and a resistor 318. The clamp circuit 310comprises, for example but not limited to, a transistor 320. The drainof the transistor 314 is connected to the pad 304, the substrate of thetransistor 314 is connected to the pad 306, and the source of thetransistor 314 is connected to the substrate of the transistor 320. Thecapacitor 316 is connected between the pad 304 and the gate of thetransistor 314, and the resistor 318 is connected between the pad 306and the gate of the transistor 314. The input terminal of the diode 312is connected to the pad 306, and the output terminal of the diode 312 isconnected to the gate of the transistor 314. The variable resistor Rv isconnected between the source of the transistor 314 and the pad 306, andmay be tuned by the diode 312. The drain D of the transistor 320 isconnected to the pad 304, the source S of the transistor 320 isconnected to the pad 306, and the gate G of the transistor 320 isconnected to the source of the transistor 314.

FIG. 3B illustrates a cross-sectional view of a semiconductor device asan embodiment of the circuit shown in FIG. 3A. Referring to FIG. 3B, inone embodiment of the present invention, the substrate comprises, forexample but not limited to, a P-type substrate, wherein the transistor320 may be an NMOS transistor comprises a gate G, a N+ doped source S, aN+ doped drain D and the P-type substrate. The diode 312 may beconstructed by, for example but not limited to, the P-type substrate andan N-well region having an N+ doped region. It is noted that, thevariable resistor Rv may be constructed by, for example but not limitedto, the substrate along the path L1 around the N-well region (as shownin FIG. 3B) that connected between the first P+ region 332 and thesecond P+ region 334. The first P+ region 332 is formed in the substratebetween the N-well region of the diode 312 and the source region of theNMOS transistor 320. The second P+ region 334 is formed in the substrateat the other side of the N-well region of the diode 312 opposite to thefirst P+ region 332. In other words, the resistance of the variableresistor Rv is dependent on the length of the path L1. In one embodimentof the present invention, the transistor 314 comprises, for example butnot limited to, an NMOS transistor. Hereinafter, the operation of theESD protection circuit 300 will be descried with reference to FIG. 3Aand FIG. 3B.

Referring to FIG. 3A, the detection circuit 308 is provided fordetecting the ESD source and the clamp circuit 310 is provided forbypassing the ESD current from damaging the IC 302, wherein the clampcircuit 310 is controlled and triggered by the detection circuit 308. Inone embodiment of the present invention, the resistance-capacitance (RC)constant (i.e., the resistance R of the resistor 318 and the capacitanceC of the capacitor 316) is much larger than the rise time of the ESDvoltage. Therefore, when a positive ESD voltage is suddenly appliedacross the pads 304 and 306, the voltage VDD is much higher than thevoltage VSS. In the meanwhile, the voltage V3 at the gate of thetransistor 314 is close to the voltage VDD since the RC constant is muchlarger than the rise time of the ESD voltage. Therefore, the voltage V3at the gate of the transistor 314 is high, and thus the transistor 314is turned on. At this moment, the high voltage V3 is also applied at theoutput terminal of the diode 312, and thus the region of the N-well isenlarged. Therefore, the resistance of the variable resistor Rv isincreased since the length of the path L1 is increased due to the changeof the N-well. Accordingly, a parasitic bipolar transistor 322 of thetransistor 320 (illustrated as the dotted lines 322 in FIG. 3B) isoperated in a forward bias condition, and the ESD current is bypassedfrom the transistor 320 of the clamp circuit 310.

Alternatively, when a negative ESD voltage is suddenly across the pads304 and 306, a parasitic diode existing everywhere in thedrain/substrate junction of the integrated circuits (IC) 302 or in theESD protection circuit 300 is forward biased and therefore is turned onto bypass the ESD current.

FIG. 4A is a circuit diagram of an ESD protection circuit according toone embodiment of the present invention. FIG. 4B is a schematiccross-sectional view of an ESD protection circuit according to oneembodiment of the present invention. Referring to FIG. 4A, the ESDprotection circuit 400 comprises, for example but not limited to, adetection circuit 408 and a clamp circuit 410. The detection circuit 408shown in FIG. 4A and FIG. 4B may be the same as the detection circuit308 shown in FIG. 3A and FIG. 3B. It is noted that, the clamp circuit410 is similar to the clamp circuit 310 except for the gate of thetransistor 420 of the clamp circuit 410 is connected to the pad 306.

Referring to FIG. 4A and FIG. 4B, as described above, when the positiveESD voltage is suddenly applied across the pads 304 and 306, a parasiticbipolar transistor 422 of the transistor 420 (illustrated as the dottedlines 422 in FIG. 4B) is operated in a forward bias condition, and theESD current is bypassed from the transistor 420 of the clamp circuit410. Alternatively, when a negative ESD voltage is suddenly across thepads 304 and 306, a parasitic diode existing in the integrated circuits(IC) 302 or in the ESD protection circuit 400 is forward biased, andtherefore is turned on to bypass the ESD current.

FIG. 5A is a circuit diagram of an ESD protection circuit according toone embodiment of the present invention. FIG. 5B is a schematiccross-sectional view of an ESD protection circuit according to oneembodiment of the present invention. Referring to FIG. 5A, an ESDprotection circuit 500 is connected between two pads 504 and 506 of theIC 502. The pad 504 is connected to a voltage VDD and the pad 506 isconnected to a voltage VSS. The ESD protection circuit 500 comprises,for example but not limited to, a detection circuit 508 and a clampcircuit 510. Both of the detection circuit 508 and the clamp circuit 510are connected between the pads 504 and 506 respectively, and the clampcircuit 510 is connected to the detection circuit 508.

Referring to FIG. 5A, the detection circuit 508 comprises, for examplebut not limited to, a variable resistor Rv, a diode 512, a transistor514, a PNP transistor 515, a capacitor 516 and a resistor 518. The clampcircuit 510 comprises, for example but not limited to, a transistor 520.The drain of the transistor 514 is connected to the pad 504, thesubstrate of the transistor 514 is connected to the pad 506, and thesource of the transistor 514 is connected to the emitter of the PNPtransistor 515. The capacitor 516 is connected between the pad 504 andthe gate of the transistor 514, and the resistor 518 is connectedbetween the pad 506 and the gate of the transistor 514. The inputterminal of the diode 512 is connected to the pad 506, and the outputterminal of the diode 512 is connected to the gate of the transistor514. The variable resistor Rv is connected between the collector of thePNP transistor 515 and the pad 506, and may be tuned by the diode 512.The drain D of the transistor 520 is connected to the pad 504, thesource S of the transistor 520 is connected to the pad 306 and the baseof the PNP transistor 515, and the gate G of the transistor 520 isconnected to the pad 506.

FIG. 5B illustrates a cross-sectional view of a semiconductor device asan embodiment of the circuit shown in FIG. 5A. Referring to FIG. 5B, inone embodiment of the present invention, the substrate comprises, forexample but not limited to, a P-type substrate, wherein the transistor520 may be an NMOS transistor comprises a gate G, a N+ doped source S, aN+ doped drain D and the P-type substrate. The diode 512 may beconstructed by, for example but not limited to, the P-type substrate andan N-well region having an N+ doped region. It is noted that, thevariable resistor Rv may be constructed by, for example but not limitedto, the substrate along the path L3 around the N-well region (as shownin FIG. 5B) that connected between the first P+ region 532 and thesecond P+ region 534. The first P+ region 532 is formed in the substratebetween the N-well region of the diode 512 and the source region of theNMOS transistor 520. The second P+ region 534 is formed in the substrateat the other side of the N-well region of the diode 512 opposite to thefirst P+ region 532. In other words, the resistance of the variableresistor Rv is dependent on the length of the path L3. In addition, thePNP transistor 515 may be constructed by, for example but not limitedto, a parasitic bipolar PNP transistor in another N-well regioncomprising a P-type substrate, a N+ doped region and the first P+ region532 as shown in FIG. 5B. In one embodiment of the present invention, thetransistor 514 comprises, for example but not limited to, an NMOStransistor. Hereinafter, the operation of the ESD protection circuit 500will be described with reference to FIG. 5A and FIG. 5B.

In one embodiment of the present invention, the resistance-capacitance(RC) constant (i.e., the resistance R of the resistor 518 and thecapacitance C of the capacitor 516) is much larger than the rise time ofthe ESD voltage. Therefore, when a positive ESD voltage is suddenlyapplied across the pads 504 and 506, the voltage VDD is much higher thanthe voltage VSS. In the meanwhile, the voltage V4 at the gate of thetransistor 514 is close to the voltage VDD since the RC constant is muchlarger than the rise time of the ESD voltage. Therefore, the voltage V4at the gate of the transistor 514 is high, and thus the transistor 514is turned on. At this moment, the PNP transistor 515 is triggered andthe leakage current of the substrate is generated. In addition, the highvoltage V4 is also applied at the output terminal of the diode 512, andthus the region of the N-well is enlarged. Therefore, the resistance ofthe variable resistor Rv is increased since the length of the path L3 isincreased due to the change of the N-well. Accordingly, a parasiticbipolar transistor 522 of the transistor 520 (illustrated as the dottedlines 522 in FIG. 5B) is operated in a forward bias condition, and theESD current is bypassed from the transistor 520 of the clamp circuit510.

Alternatively, when a negative ESD voltage is suddenly across the pads504 and 506, a parasitic diode existing everywhere in thedrain/substrate junction of the integrated circuits (IC) 502 or in theESD protection circuit 500 is forward biased and therefore is turned onto bypass the ESD current.

Accordingly, in the ESD protection circuit of the present invention,since a variable transistor tuned by a diode is provided to thedetection circuit to trigger the clamp circuit and thereby bypass theESD current, the turn-on efficiency and the shunting efficiency of theclamp circuit is enhanced. Therefore, the performance of the ESDprotection circuit is also enhanced and the power consumption of the ESDprotection circuit is reduced.

FIG. 5C is a circuit diagram of an ESD protection circuit according toanother embodiment of the present invention. FIG. 5D is a schematiccross-sectional view of an ESD protection circuit according to anotherembodiment of the present invention. The circuit shown in FIG. 5D issimilar to that of FIG. 5B except that the N+ doped region of the diode512 of FIG. 5D is connected to the second pad 506. Therefore, as shownin FIG. 5C, the variable resistor Rv is not controlled by the diode 512.However, referring to FIG. 5D, the parasitic bipolar PNP transistor 515and the variable resistor Rv can still be provided for detecting the ESDcurrent.

The foregoing description of the preferred embodiment of the presentinvention has been presented for purposes of illustration anddescription. It is not intended to be exhaustive or to limit theinvention to the precise form or to exemplary embodiments disclosed.Accordingly, the foregoing description should be regarded asillustrative rather than restrictive. Obviously, many modifications andvariations will be apparent to practitioners skilled in this art. Theembodiments are chosen and described in order to best explain theprinciples of the invention and its best mode practical application,thereby to enable persons skilled in the art to understand the inventionfor various embodiments and with various modifications as are suited tothe particular use or implementation contemplated. It is intended thatthe scope of the invention be defined by the claims appended hereto andtheir equivalents in which all terms are meant in their broadestreasonable sense unless otherwise indicated. It should be appreciatedthat variations may be made in the embodiments described by personsskilled in the art without departing from the scope of the presentinvention as defined by the following claims. Moreover, no element andcomponent in the present disclosure is intended to be dedicated to thepublic regardless of whether the element or component is explicitlyrecited in the following claims.

1. An electrostatic discharge (ESD) protection device for bypassing anESD current between a first pad and a second pad, comprising: adetection device, for detecting the ESD current, the detection devicebeing connected between the first pad and the second pad, wherein thedetection device comprises a diode and a variable resistor tuned by thediode, and an output terminal of the detection device is connected tothe variable resistor; and a clamp device, for bypassing the ESDcurrent, the clamp device is connected between the first pad and thesecond pad and connected to the output terminal of the detection device;wherein when the ESD current from the first pad or the second pad isdetected by the detection device, a trigger voltage is generated totrigger the clamp device to bypass the ESD current due to a resistanceof the variable resistor is changed by the diode.
 2. The ESD protectiondevice of claim 1, wherein the first pad and the second pad are selectedfrom a group consisting of a VDD pad and a VSS pad alternatively.
 3. TheESD protection device of claim 1, wherein the detection device comprisesa first N-type metal oxide semiconductor (NMOS) transistor comprising adrain connected to the first pad, a source connected to the outputterminal of the detection device, a substrate connected to the secondpad, and a gate connected to an output terminal of the diode, wherein aninput terminal of the diode is connected to the second pad and thevariable resistor is connected between the output terminal of thedetection device and the second pad.
 4. The ESD protection device ofclaim 3, wherein the detection device comprises a capacitor connectedbetween the first pad and the gate of the first NMOS transistor, and aresistor connected between the second pad and the gate of the first NMOStransistor.
 5. The ESD protection device of claim 3, wherein the clampdevice comprises a second NMOS transistor comprising a drain connectedto the first pad, a source connected to the second pad, a substrateconnected to the output terminal of the detection device, and a gateconnected to the substrate of the second NMOS transistor or the secondpad.
 6. The ESD protection device of claim 5, wherein the clamp devicefurther comprises a first P+ region in the substrate between the diodeand the source region of the second NMOS transistor.
 7. The ESDprotection device of claim 3, wherein the detection device comprises abipolar PNP transistor comprising an emitter connected to source of thefirst NMOS transistor, a base connected to the second pad, and acollector connected to the output terminal of the detection device. 8.The ESD protection device of claim 7, wherein the clamp device comprisesa second NMOS transistor comprising a drain connected to the first pad,a source connected to the base of the bipolar PNP transistor, asubstrate connected to the output terminal of the detection device and agate connected to the second pad.
 9. The ESD protection device of claim7, wherein the detection device comprises a capacitor connected betweenthe first pad and the gate of the first NMOS transistor, and a resistorconnected between the second pad and the gate of the first NMOStransistor.
 10. The ESD protection device of claim 1, wherein the clampdevice comprises a second NMOS transistor comprising a drain connectedto the first pad, a source connected to the second pad, a substrateconnected to the output terminal of the detection device, and a gateconnected to the substrate of the second NMOS transistor or the secondpad.
 11. An electrostatic discharge (ESD) protection circuit forbypassing an ESD current between a first pad and a second pad,comprising: a P-type substrate; a diode, comprising a first N-wellregion in the substrate and a N+ region in the first N-well region; aN-type metal oxide semiconductor (NMOS) transistor, comprising a drainregion in the substrate and connected to the first pad, a source regionin the substrate and connected to the second pad, and a gate formed overa portion of the drain region, a portion of the source region and thesubstrate there-between; and a first P+ region, formed in the substratebetween the first N-well region and the source region of the NMOStransistor, and a second P+ region formed in the substrate at the otherside of the first N-well region, wherein the gate region of the NMOStransistor is connected to the first P+ region or the second P+ regionand the second P+ region is connected to the second pad; wherein whenthe ESD current from the first pad or the second pad is detected, atrigger voltage is generated to trigger the NMOS transistor to bypassthe ESD current due to a resistance of substrate around the first N-wellis changed by the diode.
 12. The ESD protection circuit of claim 11,wherein the first pad and the second pad are selected from a groupconsisting of a VDD pad and a VSS pad alternatively.
 13. The ESDprotection circuit of claim 11, further comprising: another NMOStransistor comprising a drain region connected to the first pad, asource region connected to the first P+ region, a substrate regionconnected to the second pad, and a gate region connected to the N+region of the first N-well.
 14. The ESD protection circuit of claim 13,further comprising: a capacitor, connected between the first pad and thegate region of the another NMOS transistor, and a resistor connectedbetween the second pad and the gate region of the another NMOStransistor.
 15. The ESD protection circuit of claim 11, furthercomprising: a second N-well region formed in the substrate and includesthe first P+ region and a portion of the source region of the NMOStransistor.
 16. The ESD protection circuit of claim 15, wherein abipolar PNP transistor comprising an emitter, a base and a collector isconstructed by the first P+ region, the source region of the NMOStransistor, and a portion of the substrate under the first P+ regionrespectively.
 17. The ESD protection circuit of claim 16, furthercomprising: a capacitor, connected between the first pad and the gateregion of the another NMOS transistor, and a resistor connected betweenthe second pad and the gate region of the another NMOS transistor. 18.An electrostatic discharge (ESD) protection circuit for bypassing an ESDcurrent between a first pad and a second pad, comprising: a P-typesubstrate; a N-type metal oxide semiconductor (NMOS) transistor,comprising a drain region in the substrate and connected to the firstpad, a source region in the substrate and connected to the second pad,and a gate formed over a portion of the drain region, a portion of thesource region and the substrate there-between; a first P+ region, formedin the substrate besides the source region and opposite to the drainregion of the NMOS transistor, and a second P+ region besides the firstP+ region, wherein the gate region of the NMOS transistor is connectedto the first P+ region or the second P+ region and the second P+ regionis connected to the second pad; and a second N-well region formed in thesubstrate and includes the first P+ region and a portion of the sourceregion of the NMOS transistor; wherein when the ESD current from thefirst pad or the second pad is detected, a trigger voltage is generatedto trigger the NMOS transistor to bypass the ESD current.
 19. The ESDprotection circuit of claim 18, wherein a bipolar PNP comprising anemitter, a base and a collector is constructed by the first P+ region,the source region of the NMOS transistor, and a portion of the substrateunder the first P+ region respectively.
 20. The ESD protection circuitof claim 18, wherein the first pad and the second pad are selected froma group consisting of a VDD pad and a VSS pad alternatively.
 21. The ESDprotection circuit of claim 18, further comprising: another NMOStransistor comprising a drain region connected to the first pad, asource region connected to the first P+ region, a substrate regionconnected to the second pad, and a gate region connected to the secondpad.
 22. The ESD protection circuit of claim 21, further comprising: acapacitor, connected between the first pad and the gate region of theanother NMOS transistor, and a resistor connected between the second padand the gate region of the another NMOS transistor.